Modeling and Characterization of Inconsistent Behavior of Gate Leakage Current with Threshold Voltage for Nano MOSFETs

A strange relationship of gate leakage current and threshold voltage variation for nano MOSFETs is analyzed using factual strategy and subsequently a physical model is proffered. The gate leakage current increments with the threshold voltage before it diminishes at higher threshold voltage in nanoscale devices. This inconsistent behavior of gate leakage current with threshold voltage variations is precisely clarified in the manuscript through the concept of accord between two contrary operations: threshold voltage roll-off impact and gate leakage current reliance on surface potential. The tunneling gate leakage current density diminishes with threshold voltage over surface potential. However, the threshold voltage roll-off impact causes higher threshold voltage for larger channel length devices. The net gate leakage current is adjusted by these two contrary functions of threshold voltage. In addition, the rate of accretion of the gate leakage current with threshold voltage variation is also analyzed. The impact of the increase in the power supply voltage on the rate of accretion of the gate leakage current vs. threshold voltage curve is also explored. Thorough methodical TCAD simulations are accomplished to validate the proffered models. Both the experimental outcomes, TCAD simulations and physics based models are implemented to uncover and clarify the threshold voltage gate leakage relationship, particularly for nano MOSFETs. The proposed notion is not currently captured in conventional gate leakage nano device models, hence the proffered physical models may be utilized in progression of reliable and trustworthy TCAD simulation tools for nano devices.


Introduction
The device characteristic variations have developed as a noteworthy barrier for CMOS technology scaling [1][2][3]. Of specific significance is the factual variation of threshold voltage (V TH ) and gate leakage current (I GL ) which confines the power and performance measurements. It also prompts to critical output restrictions for both analog, digital and computerized memory/SRAM design [4][5][6]. A physical comprehension of the threshold voltage and gate leakage current (V TH )-(I GL ) relationship is critical for both device modeling and circuit design especially at nanoscale technology [7][8][9][10]. It has been noted that the (V TH )-(I GL ) relationship to a great extent has been overlooked and ignored for long channel devices, profoundly scaled 45nm and past technologies. However, the (V TH )-(I GL ) relationship cannot be ignored for nano devices, particularly for below 45nm scaled technologies. In this manuscript, we present a comprehensive study on characterizing the inconsistent behavior of gate leakage current with threshold voltage variation particularly for nano MOSFETs. The inconsistent (V TH )-(I GL ) relationship is accurately modeled after analyzing the experimental measurements and factual investigation performed on more than 20,000 MOSFETs fabricated with advanced 45nm PD-SOI technology. We evidently demonstrate that the inconsistent behavior of gate leakage current with threshold voltage variation emerges exceptionally for nanoscaled MOSFETs. Both the experimental outcomes and physics based models are acquainted to uncover and clarify the (V TH )-(I GL ) relationship particularly for nano MOSFETs.

Model Device Fabrication Approach
For the comprehensive study on characterizing the inconsistent behavior of gate leakage current with threshold voltage variation, PD-SOI MOSFETs are fabricated utilizing 45nm technology. Figure. 1 represents the typical cross-section TEM image of a N-MOSFET and P-MOSFET device used to examine and model inconsistent (V TH )-(I GL ) relationship using four discrete threshold voltage device designs (V TH1 -V TH4 ) [7]. The device development highlights the fabrication process with the following features: numerical aperture value of 1.2, 193nm immersion lithography designing, enhanced Dual-Stress Liner (DSL), Stress Memorization Technique (SMT), Advanced Annealing (AA), and close-proximity embedded advanced e-SiGe [11][12] [13][14] and estimated at V DS =V DD for V TSAT and V DS =50mV for V TLIN . The    Figure. 2 illustrates the typical threshold voltage and gate leakage current (V TH )-(I GL ) relation. The compiled data is plotted after performing simulation and extraction process on over 20,000 N-MOSFET devices from discrete lots and wafers. For V TH1 to V TH4 device lot, I GL monotonically increments with the threshold voltage inside every particular plan for V TH1 to V TH4 ; however, the accretion rate of gate leakage current diminishes with the increase in nominal threshold voltage. The characteristics are observed in both the operating regions (saturation and linear region) of the nano device. The rate of accretion of gate leakage current with the threshold voltage variations for discrete design lot (V TH1 to V TH4 ) is respectively represented by Ө 1 to Ө 4 . For precise and specific representation, Table I exhibit the simulation results  in tabular format. Table I justifies the logic when the extraction is restricted to devices of same design lot. This inconsistent behavior is visualized exceptionally for nanoscaled MOSFETs but missing in long channel devices.

Simulation Analysis and Model Formalism
A prior model on relation between threshold voltage and gate leakage current reports that the increment in threshold voltage result in augmentation of gate leakage current [10]. The obvious threshold voltage variance to the gate leakage streaming over large gate resistance leads to this conclusion that gate leakage current increments with the threshold voltage [10]. The stated notion at nano level technology node is expressly not followed in this study since the voltage drop over the post-salicide 10-finger gate is immaterial in nano devices: (1) Using the model device parameters in (1), we get 0. 1 10 ⁄ 400 40 10 1 where R s represent the gate sheet resistance, W F and L G represents the finger width and nominal gate length respectively.  (4) and (7) for the inconsistent relation between threshold voltage and gate leakage current for nanoscaled MOSFETs. To elucidate and clarify the information, a physical model is proffered which also considers the short channel impacts, prominently, threshold voltage roll-off impact as the main cause for the inconsistent (V TH )-(I GL ) relationship. The physical components for the inconsistent relation between threshold voltage and gate leakage current are viewed as two-fold contrary operations: 1) Tunneling Gate leakage current density (J GL ) The surface potential reduces with the technology node as the oxide thickness is scaled. The tunneling gate leakage current density (J GL ) diminishes with V TH over surface potential (ψ s ) similarly as shown in BSIM4 model [15]: The variables A and B are used for the simplified representation of the complicated gate leakage current density equation. The variables are equated as: The auxiliary function N inv represents the density of carriers in inversion layer of channel. It can be represented as: Using (3) in (2), the gate leakage current density can be approximated as: Here the values of the functions f, α, β are dependent barrier height (Φ b ), dielectric constant (ε OX ), electron effective mass in the dielectric (m OX ), dielectric thickness (T OX ), operating temperature (T), gate voltage (V GS ), and overdrive voltage across the dielectric (V OX ). SS is the Subthreshold Swing.
2) Threshold Voltage roll-off impact (V TH roll-off) The decline in the device threshold with the reduction in gate length is a widely known short channel effect termed as threshold voltage roll-off impact. Threshold Voltage roll-off impact causes higher V TH for longer channel length (L G ) devices. As elaborated in [16], this impact can be compactly modeled as: From (5) and (6), the gate length and the threshold voltage relation can be presented as: Here the values of η, γ variables are dependent on T OX , V DS , the minimum depletion width W DM , and the source-substrate built-in potential ψ bi . V TH0 is the long-channel device threshold voltage.
The net gate leakage current can be represented as: m s (8) Figure. 3 illustrates the proffered model (4) and (7) for the inconsistent relation between threshold voltage and gate leakage current for nanoscaled MOSFETs. The gate leakage current (I GL ) is adjusted between the previously mentioned two contrary functions of V TH . For a particular device design lot, the incline of I GL versus V TH variance relies on the initial V TH position. The slope may alter from positive to negative as elucidated through plotted TCAD simulation results. The simulation parameters used in the TCAD extraction of model (4) and (7) are listed in Table II. Figure.

Proffered Model Validation
For the proffered model validation of (4) and (7), we test the essential factors that influence the intrinsic device inconstancy regarding the (V TH )-(I GL ) relationship by experimentally decoupling the impacts of Random Dopant Fluctuation (RDF), Line-Edge Roughness (LER), and atomic-scale Oxide Thickness Variation (OTV) [1]. For the devices with the size of 400nm×10×40nm, a moderately little RDF-initiated σV TH ≈ 2.5mV is assessed in view of the TCAD simulation [4]. To assess LER and OTV independently, we channel the experimental results considering the gate length and oxide thickness. Figure. 4 demonstrates the relationship of V TLIN and T OX variance when separating the V TH1 device design lot by estimated L G =40nm, displaying that LER prompted threshold voltage roll-off impact overwhelms over the OTV impact. Figure. 4(a) demonstrates the V TLIN variance shows outwardly no association with oxide thickness (T OX ). when line-edge roughness (LER) induced threshold voltage roll-off variation is considered. However, the V TLIN variance shows positive association to the oxide thickness (T OX ). Figure. 4(b) presents the fact that the gate leakage current (I GL ) shows steady negative relation to oxide thickness (T OX ). Hence, we can conclude that the critically observed I GL versus V TLIN uncertainty cannot be primarily credited to the oxide thickness (T OX ) variance.   Figure. 5(a) and Figure. 5(b), we perceive unexpected inverse patterns, validating that threshold voltage roll-off impact plays a noteworthy part in the inconsistent threshold voltage dependent relationship between I GL and V TLIN variance especially for nanoscaled devices. The statement also supports the illustrations shown in Figure. 2. The results are also in agreement with the proffered model (4) and (7).  The rate of accretion of the gate leakage current vs. threshold voltage curve escalates with the increase in the power supply voltage. Figure. 6(a)-(d) additionally demonstrates the (I GL )-(V TLIN ) plot slope, S GL =d (I G )/d(V TLIN ) increments with the supply voltage for all the device design lot (V TH1 -V TH4 ), which is in concurrence with the proffered model (4) and (7). It presents the comparative TCAD simulation results of the gate leakage slope for V DD = 0.9V and V DD = 1V in the bar graph format. The rate of accretion of log (I GL ) vs. V TH variations for discrete design lot (V TH1 to V TH4 ) is respectively represented by Ө 1 to Ө 4 . The added subscript L/H corresponds to low/high power supply i.e. V DD =0.9V/1V. For precise and specific results, Table III represents the simulation outcomes in tabular format. It is clearly observed that the slope of (I GL )-(V TLIN ) plot increases for all four types of device designs.

Conclusion
The manuscript exhibited and proffered a physical model on the inconsistent relationship between the gate leakage current and threshold voltage variance precisely for nano scaled MOSFETs. The study and analysis presented in the manuscript has not been presently implemented in conventional gate leakage device models. The experimental results and the outcomes cannot be clarified by previously presented gate leakage models which attribute the evident threshold voltage variance to gate leakage current flowing through the gate resistance. Rather, the manuscript explores that the threshold voltage and gate leakage current (V TH )-(I GL ) characteristics can be precisely clarified and justified by short-channel impacts, in particular, the threshold voltage roll-off impact, along with a surface potential dependent gate leakage model. The tunneling gate leakage current density (J GL ) diminishes with V TH over surface potential (ψ s ). However, the threshold voltage roll-off impact causes higher V TH for larger channel length (L G ) devices. The net gate leakage current is adjusted by these two contrary functions of threshold voltage. In addition, the rate of accretion of the gate leakage current with threshold voltage variation is also analyzed. The impact of the increase in the power supply voltage on the rate of accretion of the gate leakage current vs. threshold voltage curve is also explored. Thorough methodical TCAD simulations were accomplished to validate the proffered models. Both the experimental outcomes, TCAD simulations and physics based models were implemented to uncover and clarify the Threshold voltage and gate leakage relationship, particularly for nano MOSFETs. The future nano device models ought to envelop these inconsistent (V TH )-(I GL ) characteristics enlightened in this comprehensive study to enhance the precision of gate leakage current in power proficient, multi-threshold voltage circuit design and reliability analysis.