Design of High-Performance 1-Bit Full Adder Cells Based on MOS-Type GNRFETs

In deep sub-micron technologies, conventional silicon-based transistors are faced main several problems related to the short-channel effects such as power dissipation, subthreshold leakage, and drain-induced barrier lowering (DIBL). Graphene nano-ribbon field-effect transistors (GNRFETs) have become a potential contender as a substitute for traditional silicon-based transistors in next generation nano-electronic devices. They exhibit fantastic properties such as high charge carrier mobility, mean free path of electrons, faster switching, and high ION/IOFF ratio. In order to prove the competences and superiority of these types of transistors, various circuits like full adder (FA) cells, which are the main building block of computational systems must be simulated and studied. This paper presents redesigning various 1-bit FA cells such as Complementary Metal-Oxide-Semiconductor (CMOS), Complementary Pass-Transistor Logic (CPL), Transmission-Gate (TG), Hybrid CMOS (HCMOS), and Transmission Function Adder (TFA) using MOS-GNRFET devices in 16nm technology node. Different HSPICE simulations are performed to obtain propagation delay, average power consumption, power-delay-product (PDP), and energy-delay-product (EDP) of FA cells and are compared with 16nm CMOS predictive technology model (PTM) at different supply voltages. The obtained results indicate that MOS-GNRFET based 1-bit FA cells have better performance than that of Si-CMOS one. The MOS-GNRFET based FA cells improve propagation delay and EDP at least 31.195% and 4.372%, respectively.


Introduction
Carbon-based nanomaterials are potential materials for next generations of semiconductor technology due to their extraordinary properties such as high charge carrier mobility and long mean free path of electrons [1]. Carbon nanotubes (CNTs) and graphene are two of the most studied allotropes of carbon [2], which exhibit the same properties [3]. However, graphene has received much attention because of its planar structure, so it does not need major technological shift [4]. Graphene is a single atomic layer of carbon film with two-dimensional honeycomb lattice, has no intrinsic bandgap and hence cannot be completely turned ON or OFF [5]. With tailoring the graphene to one-dimensional (1-D) graphene nanoribbons (GNRs) form with width less than 10 nm, a bandgap opens up and can be used as channel material [6]. GNR field effect transistors (FETs) (GNRFETs) are potential substitution for silicon-based transistors due to faster switching, reduced short channel effects, lower energydelay product (EDP), and high I ON /I OFF ratio [5,7].
Full Adders (FAs) are main core of arithmetic operations in digital systems such as arithmetic and logic unit (ALU), microprocessors, and application-specific digital signal processing (DSP) architectures [8,9]. In this paper, five various 1-bit FA cells based on MOS-GNRFET and Si-CMOS transistors are designed and simulated in the different supply voltages. These include Complementary Metal-Oxide-Semiconductor (CMOS), Complementary Pass-Transistor Logic (CPL), Transmission-Gate (TG), Hybrid CMOS (HCMOS), and Transmission Function Adder (TFA). The rest of the paper is organized as follows. Graphene and GNRFETs are described in section II. Five various 1-bit FA cells used in this paper are defined in section III. In section IV, the simulation results and the discussions are presented.
Finally, section V concludes this study.

Review of Graphene and GNRFETs
Graphene is a zero-gap semi-metal in nature and transistors fabricated by that have a low I ON /I OFF ratio, and hence is not suitable for digital applications [5]. With converting the graphene into narrow strips, which are called GNRs with width < 10 nm, a bandgap opens up and can be used as a channel material in FETs [10]. Based on the edge geometry, there are two types of GNRs: 1) Zigzag-GNR (ZGNR) and 2) Armchair-GNR (AGNR). The ZGNR always acts as a metal, while the AGNR can have both metal and semiconductor properties [6]. The energy gap of graphene is in inverse proportion to its width [11]. On the other hand, the number of dimer lines (N) determines the GNR width (W CH ), which is in direct ratio to it. The following equations exhibit the dependency of W CH and gate width (W GATE ) on N [5].

√3
(1) is the distance between two adjacent GNRs within the same device, and is the number of ribbons. According to the three-periodic trend of N, for $ 3%, $ 3% 1, and $ 3% 2 (p & N), the bandgap is moderate, large, and small, respectively [12].
Based on the FET design, GNRFETs are of two types: 1) Schottky barrier (SB)-GNRFET (SB-GNRFET) and 2) MOS-GNRFET. SB-GNRFETs have a GNR-based channel and metalbased contacts, which SBs occur at the graphene-metal junctions. On the other hand, MOS-GNRFETs consist of a GNR-based channel and heavily doped source and drain reservoirs [13]. These doped reservoirs lead to a higher I ON /I OFF ratio and hence perform better than SB-GNRFETs. Other major advantages of MOS-GNRFET over the SB-GNRFETs are faster switching, resulting in smaller delay, and higher trans-conductance [14], hence we used the MOS-GNRFET to design the 1-bit FA cells. The structure of MOS-GNRFET is shown in Figure 1. The use of multiple parallel GNRs in the device leads to its drive strength increases. The used GNRs are armchair-type due to its semi-conducting property [6].

The 1-Bit Full Adder Cells
The 1-bit FA cells are the main component of computational circuits and extensively used in digital electronic systems like microprocessors. The limitations of FA cells design include small area, high-speed, lower power consumption, and high-throughput [15]. The 1-bit FA cells get three 1-bit inputs A, B, C in and give two 1-bit outputs Sum and C out , which relate together as follows: , ./0 ) · + , -· ) * + Five different 1-bit FA cells are selected in this paper, which are described in the following [8,9]: 1) The CMOS FA cell utilizes 28 transistors to implement the equations (3) and (4). It is designed based on mirror structure (pull-up and pull-down transistors).

The Simulation Results and Discussion
In order to simulation of MOS-GNRFET based 1-bit FA cells in HSPICE software, we used the SPICE-compatible model of GNRFET, which is developed in [5]. Table 1 indicates the various MOS-GNRFET parameters. Five different 1-bit FA cells selected in the previous section are analyzed at a frequency of 125 MHz, and with ±10% variations at the nominal supply voltage of 0.5 V. The simulations are performed by adding buffers in the input and output sides, load capacitance of 15 fF, at a temperature of 27 ˚C. The Si-CMOS based transistor sizing has been taken from [8,9], and based on this sizing the number of GNRs ( ) in MOS-GNRFET has been selected to be equal to Si-CMOS in terms of area. In table 1 n ribb is the number of graphene nanoribbons and % is the probability of losing an atom on the edge of a GNR due to incomplete fabrication, which is called line-edge roughness probability [5]. Table 2 shows the values of worst-case delay and average power consumption of both MOS-GNRFET and Si-CMOS based on all five types of 1-bit FA cells in the different supply voltages. We applied all possible states of the inputs to the cells and then measured the delays as the time duration from 50% of inputs to 50% of outputs. Finally, their worst is reported. From this table, the MOS-GNRFET based 1-bit FA cells (denoted by G-(FA cell name)) show an impressive reduction in the worst-case delay compared to Si-CMOS one and provide FA cells with high-speed performance. The average power consumption of the MOS-GNRFET based TFA and CMOS FA cells is less than Si-CMOS ones. The designing CPL FA cell using MOS-GNRFETs consumes lower average power compared to Si-CMOS at supply voltages of 0.45 V and 0.5 V. Table 3 exhibits the values of PDP and EDP for all five types of 1-bit FA cells using MOS-GNRFET and Si-CMOS transistors in three supply voltage values. The results indicate MOS-GNRFET based FA cells have lower EDP than Si-CMOS one, which is very useful for energy-efficiency applications. In addition, all MOS-GNRFET based FA cells have lower PDP than that of Si-CMOS ones, except HCMOS FA cell at supply voltages of 0.5 V and 0.55 V. Figure 2 shows the bar graph for the worst-case delay, average power, PDP, and EDP of both MOS-GNRFET and Si-CMOS-based 1-bit FA cells in the different supply voltages. It is observed from these figures that designing 1-bit FA cells using MOS-GNRFETs is much better than Si-CMOS. Therefore, MOS-GNRFETs can be a potential replacement for Si-CMOS based transistors in the future scaled technologies.

Conclusion
This paper presents the designing five various 1-bit FA cells such as CMOS, CPL, TG, HCMOS, and TFA using MOS-GNRFET and Si-CMOS transistors. These FA cells are simulated in HSPICE software by ±10% changing at the nominal supply voltage of 0.5 V to obtain values of their main performance metrics such as worst-case delay, average power, PDP, and EDP. The results show that all five types of MOS-GNRFET designs have lower worst-case delay and EDP, which provide the devices with high-speed and energy-efficiency performances. The designing CMOS and TFA FA cells using MOS-GNRFETs have lower average power consumption in all three supply voltage values compared to Si-CMOS ones. All types of MOS-GNRFET based FA cells except HCMOS FA cell have lower PDP than that of Si-CMOS based FA cells.