Scrutiny of Leakage Currents with Insulating Materials for Transistor Applications

Continuous reducing the size of transistor technology has enabled extraordinary improvements in the switching speed, density, functionality and cost of microprocessors. Integrated Circuit industry is pursuing Moore’s curve down to deepnanoscale dimensions. Advanced transistor technology now faces many challenges that together result in static power consumption due to leakage currents. In fact, leakage currents are responsible for more than 50% of the total power consumption in nanoscale designs. In deep-nanoscale arena, this percentage will increase further. However, diagnosing of the interface quality and interaction between insulators and semiconductors is significant to reduce the leakage current and achieve the high performance of switching devices in the nanoscale domain. Continuous scaling down has required drastic decreases of the SiO2 dielectric film thickness to achieve ever-higher capacitance densities. Fundamental limits of SiO2 as a dielectric material, imposed by electron tunneling, will be reached as this SiO2 film thickness approaches ~1nm. Therefore, alternate high-k interlayer dielectric material will be needed to replace SiO2 as a capacitor and gate dielectric material. Numerous alternate high-k materials are being actively investigated, ranging from Al2O3 (k ~ 9) to HfO2 (k ~ 25). High-k materials hold the promise of achieving very high capacitance densities with relatively thick films.


Introduction
The semiconductor microelectronics and nanoelcectronics industry requires interlayer dielectric films for a variety of applications [1]. Dielectric layers are needed as gates in 2-D nanostructures, graphene, hexagonal boron nitride (h-BN), and more recently the rich family of transition metal dichalcogenides (TMDs) comprising molybdenum disulphide (MoS 2 ), WS 2 , WSe 2 , as capacitors to store charge in memory devices, and as insulation in back-end interconnects [2][3]. Silicon dioxide (SiO 2 ) has been the dielectric material of choice for all of these applications. Silicon dioxide (SiO 2 ) is a dielectric material with very low leakage currents, acts as a good diffusion barrier for dopants and ionic contaminants, and forms a well-defined interface with silicon. The continued drive towards faster processors has required the progressive shrinking from microelectronics to nanoelcectronics devices [1]. The decrease in device feature size allows for increased speed, lower power consumption, and lower cost because of the increased density of devices per wafer. This size reduction presents challenges for the various SiO 2 applications. The insulation of interconnects requires lower dielectric constant materials. Applications such as capacitors and gate dielectrics require higher dielectric constant materials. Decreasing the thickness of the SiO 2 dielectric film achieves the goal of increasing the capacitance to offset the decrease in the surface area of the capacitor. However, SiO 2 films will soon need to be so thin that tunneling through the film will become significant and will increase power consumption to unacceptable levels.
High-k materials are needed to replace SiO 2 in these applications to achieve high capacitances while keeping the leakage currents low [4][5].
As devices approach the sub-45 nm scale, the effective oxide thickness (EOT) of the traditional silicon dioxide Materials for Transistor Applications dielectrics are required to be smaller than 1 nm, which is approximately three (3) monolayers and close to the physical limit, thus resulting in high gate leakage currents due to the obvious quantum tunneling effect at this scale [25]. To continue the downward scaling, dielectrics with a higher dielectric constant (high-k) are being suggested as a solution to achieve the same transistor performance while maintaining a relatively thick physical thickness. Many candidates of possible high-k gate dielectrics have been suggested to replace SiO 2 and they include nitride Si 3 N 4 , Hf-based oxides, and Zr-based oxides. Hf-based oxides have been recently highlighted as the most suitable dielectric materials because of their comprehensive performance in order to continue manufacturing low-cost semiconductor products, its dimension and concentration, like oxide thickness and substrate profile and device structure [6][7]28].
The rest of this paper is organized as follows. Section II discuss about the requirement for transistors in the context of memory and gate applications. Various emerging dielectric materials are discussed in Section III. Section IV shows the effect of insulating materials on leakage currents. Finally, a summary and conclusion is drawn by Section V.

Requirements for Memory and Gate Applications
Memory capacitor and gate applications both need alternate high-k dielectrics to achieve higher capacitance densities [27]. However, the requirements for memory capacitor and gate applications are different [1]. Capacitors for memory need very low leakage currents density on the order of 10 -8 A/cm 2 . This requirement allows the charge stored in the capacitor to remain large enough to be read for a relatively long time period, typically ~250 ms [18]. In contrast, the nature of the high-k/electrode interface is not that critical, provided that the interface does not reduce the capacitance significantly. Metal or highly doped nitrided poly-Si may be used as the electrodes. High-k dielectrics grown by atomic layer deposition. Gate dielectrics in FETs can have a much higher leakage current, but the quality of the high-k/Si bottom electrode interfacial region is critical [1]. Current densities as high as 1-10 A/cm 2 are acceptable for some processors. Certain low power applications, such as portable devices, demand leakage currents of < 10 -3 A/cm 2 . These leakage current levels are still much less stringent than the requirements for memory capacitors. More important to the performance of an FET is the electric field that penetrates into the silicon channel. Interfacial layers and interface roughness adversely affect the strength and uniformity of this electric field and degrade FET performance [1].

High-k Dielectric Materials
Most of the known binary metal oxide high-k materials have been grown by ALD. These binary metal oxide materials include, approximately in order of increasing dielectric constant, Al 2 O 3 , Si 3 N 4 , ZrO 2 , HfO 2 , and TiO 2 . The dielectric constants of these thin films grown by ALD range from k~10 to k~100. These dielectric constants are comparable with the dielectric constants measured for the same materials grown by other methods. In this section, a literature survey on five oxide material are given and a comparative study is shown in Table 1.

Aluminium Oxide (Al 2 O 3 )
Alumina is the more common name of Aluminium Oxide (Al 2 O 3 ) and is a hard wearing material used for many applications. Once fired and sintered, it can only be machined using diamond-grinding methods. Aluminium oxide is an electrical insulator but has a relatively high thermal conductivity (40 W/m K). In its most commonly occurring crystalline form, called corundum, its hardness makes it suitable for use as an abrasive and as a component in cutting tools. Aluminium oxide is responsible for metallic aluminium's resistance to weathering. Metallic aluminium is very reactive with atmospheric oxygen, and a thin passivation layer of alumina quickly forms on any exposed aluminium surface. This layer protects the metal from further oxidation. The thickness and properties of this oxide layer can be enhanced using a process called anodising. A number of alloys, such as aluminium bronzes, exploit this property by including a proportion of aluminium in the alloy to enhance corrosion resistance. The alumina generated by anodising is typically amorphous, but discharge assisted oxidation processes such as plasma electrolytic oxidation result in a significant proportion of crystalline alumina in the coating, enhancing its hardness.

Silicon Nitride (Si 3 N 4 )
Silicon nitride-based ceramics have many excellent properties, high strength and relatively high fracture toughness, good wear resistance, good oxidation resistance and good corrosion resistance. For some time, they have been under consideration as high-performance structural materials because of their superior thermal shock resistance relative to oxide ceramics [8]. Silicon Nitride has been densified with sintering additives because of the highly covalent Si-N bonding. After sintering, these additives remain as the amorphous grain boundary phase, which severely deteriorates the high-temperature mechanical behavior of Silicon Nitride ceramics [9]. Dielectric films of silicon nitride ceramics play an integral role in nearly every semiconductor device and integrated circuit. Among this Silicon Nitride ceramic is used as a gate dielectric layer, diffusion barrier and optoelectronic-integrated circuits [10]. Low-density porous silicon nitride [11] ceramic is an important material with properties including low dielectric constant, good mechanical, high resistance to rain erosion and sand erosion. Hence, low-density porous silicon nitride ceramic is also a candidate for application in radome materials. Microstructural control of the interface and interlayer requires a complex interplay between initial composition and post-heating transformations. Nowadays most silicon nitride ceramics are prepared using α-Si 3 N 4 powders. In silicon nitride ceramics, the microstructure is similar to whisker-reinforced ceramic composites, with large rod like β-Si 3 N 4 grains as the reinforcing agents [12].

Zirconium Oxide (ZrO 2 )
Zirconium oxide (ZrO 2 ) has attracted much attention as a high-K material because of its high temperature stability and high mechanical strength [13]. Thin films of ZrO 2 can be prepared by many methods like sol-gel, spin coating, ALD, reactive sputtering, MOCVD, E-beam evaporation, pulse laser ablation, and rapid thermal CVD [14]. Unfortunately, oxides of zirconium (ZrO 2 ) tend to crystallize much more rapidly than SiO 2 , which makes the interface surface rough. So the key issue will be to form amorphous oxides of the metal initially, which might transform into the crystalline state during thermal cycling. One current avenue of investigation is to incorporate silicon (Si), Al, or N 2 into the random network structure [15]. Indeed, adopting the above theory, zircon (ZrSiO 4 ), a compound of ZrO 2 and SiO 2 , has shown better interface behavior with silicon (due to its dangling bonds) and has provided more symmetric band alignment with much higher conduction band offsets compared to ZrO 2 (2.10 eV compared to 0.64-1.2 eV of ZrO 2 ).

Hafnium Oxide (HfO 2 )
Among the various requirements of gate dielectric materials, the most important are good insulating properties and capacitance performance. Because the gate dielectric materials constitute the interlayer in the gate stacks, they should also have the ability to prevent diffusion of dopants such as boron and phosphorus and have few electrical defects which often compromise the breakdown performance. Meanwhile, they must have good thermal stability, high recrystallization temperature, sound interface qualities. With regard to capacitance performance, the requirement is that the k value should be over 12, preferably 25-30. An appropriate k value means that the dielectrics will have a reasonable physical thickness which is enough to prevent gate leakage and not too thick to hamper physical scaling when achieving the target EOT. CVD and ALD deposited oxides (HfO 2 ), silicates (HfSiOx and HfSiON) and aluminates of hafnium (Hf) show higher k and lower leakage current than SiO 2 at the same EOT. The materials also offer a higher limiting offset barrier (0.5 eV) [16] besides being stable thermodynamically and electrically over silicon (Si) at high temperatures [17]. At the same time silicon dioxide and oxynitride, the traditional gate dielectric materials in field effect transistors (FETs), are rapidly approaching their ultimate thickness.

Figure 2. Major leakage mechanisms in MOS transistor.
Leakage current is dominated by subthreshold leakage, gate-oxide tunneling leakage and reverse-bias pn-junction leakage for nanoscale device like silicon technology based transistor and/or polycrystalline solar cell [21,29]. Those three major leakage current mechanism are illustrated in Figure 2. There are still other leakage components, like gate induced drain leakage (GIDL) and punch through current, however, those ones can be still neglected in normal operation of digital circuits [19,[25][26].

Subthreshold Current
Supply voltage has been scaled down to keep dynamic power consumption under control. To maintain a high drive current capability, the threshold voltage (Vth) has to be scaled too. However, the Vth scaling results in increasing subthreshold leakage currents. Subthreshold current occurs between drain and source when transistor is operating in weak inversion region, i.e., the gate voltage is lower than the Vth. The drain-to-source current is composed by drift current and diffusion current. The drift current is the dominant mechanism in strong inversion regime, when the gate-tosource voltage exceeds the Vth. In weak inversion, the minority carrier concentration is almost zero, and the channel has no horizontal electric field, but a small longitudinal electric field appears due the drain-to-source voltage. In this situation, the carries move by diffusion between the source and the drain of MOS transistor. Therefore, the subthreshold current is dominated by diffusion current and it depends exponentially on both gateto-source and threshold voltage. The subthreshold leakage current [20] for a MOSFET device can be expressed as (1), where I Wμ C V " # e $.& L ( , V " kT q ( is the thermal voltage, V is the threshold voltage, V and Vare the drain-to-source voltage and gate-to-source respectively, W and L are the effective transistor width and length and n is the subthreshold swing coefficient.

Gate Oxide Tunneling Current
Aggressive scaling of the oxide thickness, in turn, gives rise to high electric field, resulting in a high direct-tunneling current through transistor gate insulator. The tunneling of electrons (or holes) from the bulk and source/drain overlap region through the gate oxide potential barrier into the gate (or vice-versa) is referred as gate oxide tunneling current. This phenomenon is related with the MOS capacitance concept. There are three major gate leakage mechanisms in a MOS structure. The first one is the electron conduction-band tunneling (ECB), where electrons tunneling from conduction band of the substrate to the conduction band of the gate (or vice versa). The second one is the electron valence-band tunneling (EVB). In this case, electrons tunneling from the valence band of the substrate to the conduct band of the gate. The last one is known as hole valence-band (HVB) tunneling, where holes tunneling from the valence band of the substrate to the valence band of the gate (or vice-versa). Each mechanism is dominant or important in different regions of operation for NMOS and PMOS transistors. For each mechanism, gate leakage current can be modeled by [21,23]. ? (2) where W and L are the effective transistor width and length, respectively. A = q @ 16π # hϕ ⁄ , B = 4πH2m ϕ @ # ( 3ℏq ( , m is the effective mass of the tunneling particle, ϕ is the tunneling barrier height, t is the oxide thickness, ℏ is reduced Planck's constant and q is the electron charge.

Band-to-Band Tunneling Current
The MOS transistor has two pn junctions -drain and source to well junctions. These junctions are typically reverse biased, causing a pn junction leakage current. This current is a function of junction area and doping concentration. When 'n' and 'p' regions are heavily doped, band-to-band tunneling (BTBT) leakage dominates the reverse biased pn junction leakage mechanism. A high electric field across a reverse biased pn junction causes a current flow through the junction due to tunneling of electrons from the valence band of the p-region to the conduction band of the n-region. Tunneling current occurs when the total voltage drop across the junction, applied reverse bias NV /OO P plus built-in voltage Qψ S T, is larger than the band-gap. The tunneling current density through a silicon pn junction is given by [21], where C = H2m * q @ 4π @ ℏ # ⁄ , and D = 4√2m * 3ℏq ( , m * is the effective mass of electron; Eis the energy-band gap; V /OO is the applied reverse bias; ε is the electric field at the junction; q is the electron charge; and ℏ is reduced Planck's constant.  Band-to-band tunneling leakage, negligible in current processes when compared to the subthreshold and gate oxide leakages, starts to be taken into account in 25nm technologies [22,24].

Summary and Conclusion
Scaling of device dimensions has historically made advances in silicon ULSI technology. As a result of this scaling, both the vertical and horizontal dimensions have been reduced to a point where silicon dioxide as a dielectric material cannot satisfy the requirements. The many benefits driving manufacturers to use low-k dielectric materials include increased device speed, reduced power, required heat dissipation, and reduced interline talk. However, the transition to low k has been delayed primarily because of challenges in their integration, including etching and stripping problems associated with the carbon content materials.
Low-K materials in general exhibit weak polarization when subjected to an external electric field. There are several guidelines in formulating these materials; the most obvious one is the choice of a non-polar dielectric system. In these materials, polarity is weak because of symmetrical polar chemical groups that cancel the dipoles of chemical bonds between dissimilar atoms.
In the case of high-k materials, scaling the thickness of the gate dielectric has long been recognized as one of the keys to scaling devices. It is expected that for sub100 nm devices (CMOS) the gate oxide will be less than 2 nm. Thus it appears that SiO 2 will be unsuitable as a gate insulator in the sub-100 nm device. The vertical scaling requirements for gate stacks and for shallow extension junctions require 1 nm equivalent oxide thickness (EOT) to deal with leakage current tunneling. Some metal oxides, like HfO 2 , ZrO 2 and their silicates, have been identified as promising materials that are supposed to work with 1 nm EOT. However, integration of high-k Oxide Thickness (nm) Total leakage Current (A/m 2 ) TiO2 Al2O3 Si3N4 ZrO2 HfO2 materials will be a challenging task because of the chemical bonding (ionic) and are likely to exhibit both ionic conduction and high charge levels.
The limited chemical and thermal stability are the two most important criteria associated with alternative high-k dielectrics and alternative gate electrode materials. In spite of the advantages of the polysilicon gate, the present process flow to integrate the future advanced gate stack employing these high-k materials is still questionable. Thus new integration schemes and device structures may be required to form source/drain junctions of MOS and all high temperature processes are to be done before the formation of the gate stack. At the same time, the chemical mechanical polishing (CMP) process used to planarize the surface has several advantages and challenges. The challenges include identifications of suitable materials for sacrificial gate stack and spacers and development of the consumables. Although several high-k materials and processes have been investigated, it still appears that the major concern is the cost.