CMOL Based Quaded Transistor NAND Gate Building Block of Robust Nano Architecture

Nano architectures are more prone to defects. This work is aimed at finding the effectiveness of using quaded structure devices to improve the reliability of logic gates in Nano lavel. Transistor level redundancy (Quaded Structure) has been applied in a CMOS gate (NAND) design to improve the reliability. Being an universal gate, NAND gate can be the building block for nano architecture. CMOL is a hybrid architecture that combines conventional CMOS and Nano architecture together. Based on CMOL, a NAND gate design has been proposed. To study the performance of the proposed architecture, theoretical analysis has been proposed. Moreover, to evaluate the effectiveness of the quaded structured NAND (QNAND) gate, detailed simulation was carried out. Simulation results illustrates that quaded structured design achieves significantly higher defect tolerance by enhancing the reliability of the QNAND gate.


Introduction
Nano+Micro hybrid architecture is an integration of nanowire crossbars with CMOS circuits. This hybrid architecture provides ultra-dense integration of devices and interconnects. So the performance with respect to speed, power and area, is superior to nano or micro architecture alone. CMOL ("CMOS + NANOWIRES + MOLECULES") developed by Likharev et. al [1], combine CMOS logic elements with nanowire crossbar arrays similar to Field Programmable Gate Arrays (FPGA).
In nano scale, there are uncertainties due to inherent characteristics of the devices, stochastic nature of fabrication process and external disturbance. These uncertainties are the source of faults in nano level. Popular self assembly fabrication processes have probabilistic nature which result in a fairly large percentage of defective devices. Due to small cross section areas of wires, they become fragile. Moreover, the contact area between nanowires and between nanowires and devices depends on a few atomic-scale bonds. For these reason, some connections become poor and effectively unusable [2,3,4]. In comparison with the failure rate of conventional CMOS (approximately 10 -7 -10 -6 ), the failure rates of nano scale devices are just under unity. These devices are more sensitive to external disturbances, such as radiation effects, electromagnetic influence, parameter fluctuations, and high temperatures. In addition, process variations introduced due to uncertainty and complexity of nanoscale device fabrication process can affect leakage dissipation, power consumption, reliability, and defect [5,6,7]. Hence permanent and transient [8] faults or defects will occur during the manufacturing phase and during the field operation due to such factors as aging, while transient faults will appear in the field due to external disturbances.
Redundancy-based defect tolerance techniques can tolerate against both permanent and transient faults. [15] proposesan architecture for a silicon-based quantum computer processor based entirely on complementary metal-oxide semiconductor (CMOS) technology, which is the basis for all modern processor chips. Redundancy can be added at the transistor level, gate level or functional block level. If the most fundamental component of a design (i.e. transistor) are made more robust by using redundancy, it will improve the design reliability more when compared with defect tolerance techniques applied at higher level of abstraction (block level or functional level). Adding redundancy at the transistor level is less costly in terms of overhead when compared with the same defect tolerance techniques applied at higher level (block or functional). Adding redundancy at lower level of the design abstraction is a promising technique and merits further consideration and research. [16] presents a Single Event Upset (SEU) robust low phase-noise PLL for clock generation in harsh environments like nuclear and space applications. The PLL has been implemented in a 65 nm CMOS technology. [17] introduces a new approach to design fault-se-cure encoder and decoder circuitry for memory designs. The key novel contribution of this paper is identifying and defining a new class of error-correcting codes whose redundancy makes the design of fault-secure detectors (FSD) particularly simple. [18] develops a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer.

Quadded Transistor Structure
Defect tolerance can be improved by adding redundancy at transistor level. In Quadded Transistor logic each transistor of a circuit is replaced by a quadded transistor structure as shown in figure 1

CMOL Circuit Architecture
The basic idea of CMOL circuits is to combine the CMOS technology with molecular-scale two-terminal nano devices. The advantages of CMOS are its flexibility and high fabrication yield. The nano devices have extremely high potential density. CMOL fabrication costs may be at affordable level due to relatively large critical dimensions of CMOS components and the "bottom-up" approach to nano device fabrication. At the same time, the density of active devices in CMOL circuits may be as high as 10 12 per cm 2 and that they may provide an unparalleled information processing performance, up to 10 20 operations per cm 2 per second, at manageable power consumption.
CMOL circuits consist of two levels of nanowires. At each cross point of a "crossbar" array, Nano devices are formed by self-assembling (figure 2). The CMOS/nanodevice interface problems are overcome in CMOL circuits by providing interface pins that are distributed all over the circuit area, on the top of the CMOS stack. (Silicon-based technology necessary for fabrication of pins with nanometer-scale tips has been already developed in the context of field-emission arrays [9].) As Figure 1c shows, There are two types of pin, reaching to either the lower or the upper nanowire level. Pins of each type are arranged into a square array with side 2 β F CMOS . Here F CMOS is called the half-pitch of the CMOS subsystem. Β is a dimensionless factor whose value is larger than 1 and it depends on the CMOS cell complexity. The nanowire crossbar is turned by angle α =arcsin (F nano /β F CMOS ) relative to the CMOS pin array, where F nano is the nano wiring half-pitch [10].
Two nanowires which have contact with two pins may be connected to CMOS data lines by activating two pairs of perpendicular CMOS lines, (figure 2b). As Figure 1c illustrates, this approach allows a unique access to any nano device, even if F nano « F CMOS [10].

Configuration by CMOL FPGA
Strukov described the configuration of simple NOR gate by CMOL FPGA [11]. CMOS inverters together with pass transistor and nano devices were used to form the basic 'wired-NOR' gates ( figure 3). The pass transistors were used as pull-down resistors, while the nano devices set into ON (low-esistive) state were used as pull-up resistors. For example, if only the two nano devices shown in figure 3(b) are in the ON state, while all other latches connected to the input nanowire of cell F are in the OFF (high resistance) state, then cell F calculates the NOR function of signals A and B [11].

Proposed Configuration of NAND Gate
Similarly we proposed the configuration of CMOL based NAND gate. If any one of the nano devices are in OFF (high resistance) state, then cell F calculates the NAND function of signals A and B figure 4.

Electrical Model of the Proposed Configuration
According to Strukov's model [11], nanowires within a layer are separated by a distance equal to their width. Let the nanowire width is 15 nm, a switching layer separating the two nanowire layers is 3 nm thick and there is an insulator between and around all nanowires with a dielectric constant of 3.9 (that of SiO 2 ). Then according to the Strukov's model we can predict a capacitance per length of approximately 2.8 pF cm −1 . We can choose a material having a lower dielectric constant around 3.5 as a passivation layer covering the top nanowire layer that protects the nanowire layers. Nanowire pads add additional capacitance that can be neglected since their area is quite small compared to that of the nanowires. From these considerations we can estimate the nanowire capacitance at 2.0 pF cm −1 [11].
The effective resistivity of the the nanowire material decides the resistance per unit length of nanowire. According to Strukov's model, we also assume here that the nanowirers are copper nanowirers (the metal specified in the ITRS roadmap). For example, Cu wires with a line width of 15 nm are projected to have an effective resistivity of approximately 8 µΩ cm, so a square Cu nanowire, 15 nm on a side, would have a resistance of about 355Ω µm −1 .
It is difficult to model nanowire resistivity, ρ, for very small (<10 nm) wires. A common approximation by Strukov [11] was Here p is the fraction of electrons scattered specularly at the surface and is assumed to be 0.67, λ (the mean free path) is equal to 40 nm, ρ 0 (the bulk resistivity) is equal to 2 µΩ cm, and d is set to the nanowire width. But this model does not reflect properly the effective resistivity for small wires [12] and assumes negligible increased resistivity due to scattering at grain boundaries (which is possible for very large grain sizes). According to Snider [13] we fitted the resulting model to the ITRS resistivity model, finding a reasonable fit for p = 0.6 and a grain boundary reflectivity coefficient of 0.43. For 30 nm pitch nanowires, we have chosen closed-junction resistance value as 24 kΩ.
The projected n-FET switching time was 0.39 ps for the year 2010 from the ITRS roadmap [14]. Accordingly the CMOS gate delay was estimated t 10 ps. Circuit timing is strongly dominated by the RC delays of the nanowires.
According to Strukov's model [11] the average total power consumption of a CMOL gate may be estimated as a sum of Static power P ON due to currents I ON , ≈ Static power P leak due to current leakage through nano devices in their OFF state, Dynamic power P dyn due to recharging of nanowire capacitances.

= (4)
Where τ is the total circuit delay. The factors 1/2 reflect the natural assumption that on average there is an equal number of CMOS inverters with Boolean 1 and 0. The dynamic power has an additional factor 1/2 describing the energy loss at capacitance recharging. Figure 5 shows the electrical model of nano wires and junctions of nano wires. According to Snider [13], (a) shows the electrically closed junction switches between the nanowire driven by the source and the two nanowires connected to the sinks. The electrical model (b) shows the physical coordinates of the nanowires and their closed junctions to derive nanowire resistance and capacitance.

Performance Testing
As discussed before, qNAND is special structure consisting of four Metal Oxide Semiconductor (MOS): two PMOS and two NMOS where four replica is used instead of only one element. Following figure 6 shows the layout of proposed qNAND. It's a two input one output NAND gate of quaded structure. Nand gate behaves as opposite to AND gate. In the following figure 6, there are two input A and B and corresponding output is shown. White color represents input A and green color represents input B and output is in red color. From the truth table of NAND gate we know that, if at least one input is low (0), output will be high (1). If both input is high (1) output is low (0). For example, in the time period of 0.6 ns, input A is low but input B is high resulting the output to be high. But in time period of 0.8 ns, both input A and B is high and the output is low. So, it is clear that, proposed qNAND gate is working correctly.  For implementing fault tolerant voter circuit, we have used quaded structure NAND gate. To asses it's performance against different faults, proposed QNand is tested with various fault models such as stuck at 0, stuck at 1, bridging fault model.

Testing with Stuck at 0 Fault
Stuck at 0 is a basic fault model for testing performance of any design. In such cases, particular elements are set to be open. As a result the whole component fails to operate correctly. However, in the proposed qNAND, four transistor is used instead of one for increasing fault tolerance.
If the defects do not occur in any two parallel transistors, double stuck open or their corresponding bridge defects are tolerated. In the figure 7 (a), layout stuck at 0 fault is applied, transistor 1 and transistor 3 are set open thus stucking at a value of 0 all the time. As these two transistors are in series this fault is tolerable and correct output is given in figure  7(b).
On the other hand, double stuck open or their corresponding bridge defects are not tolerated if defects occurs in any two parallel transistors. In the figure 8 (a), transistor 1 and 2 are in parallel and opened thus stucking at 0 all time. As a result, circuit will fail to operate correctly. In the figure 8 (b), output of this fault injected QNand is shown.

Testing with Stuck at 1 Fault
Double-stuck short or their corresponding bridge defects are tolerated as long as they do not occur to any series transistors. This is shown in figure 9 (a) and figure 9 (b). Here, transistor 1 and 2 are shorted. As a result, both of the transistor are stuck at 1 throughout the period. But still now the QNand is providing correct output.
But if defects occurs in any two series transistors Doublestuck short or their corresponding bridge defects are not tolerated. This is shown in figure 10 (a) and figure 10 (b). Transistor 1 and transistor 3 are in series and they are shorted. Thus these transistors are stuck at 1 throughout the time period. So double stuck short and bridge defects are not tolerated in this case.
However, it may be concluded that, proposed Quaded Nand architechture (QNAND) is completely fault tolarable for single defect cases. But for double defect cases, it is fault tolerable fulfilling some conditions.

Conclusion
In this work, the feasibility and effectiveness of quaded transistor structure has been investigated as a defect-tolerant technique at nano level. The proposed technique was found reliable against many permanent defects including stuck-open, stuck-short and bridging defects. Experimental results have demonstrated that the proposed technique provides significantly less circuit failure probability and higher reliability. The results have been investigated theoretically and by simulation.
Also, a suitable architecture has been proposed for NAND gate to be implemented in nano level. The CMOL based hybrid (NANO/CMOS) architecture is very much applicable for future electronics that has the capability to merge the existing CMOS level to future nano level.