Efficient Sign-Detection-Scheme Using Modular Computation Technique for the Moduli Set {2 n -1, 2 n , 2 n +1, 2 (n+1) -1, 2 2n -5}

: In computer arithmetic, one of the most important things to consider in hardware design is the ability of the system to detect and display numbers with their signs. This when properly managed will reduce errors and ensure hardware reliability. But interestingly, detecting and knowing the sign of a residue number during arithmetic operation is very difficult. Magnitude Comparison, Scaling and Number conversions are some of the other difficult operations in Residue Number System (RNS). Unlike the weighted number system, it is even extremely difficult to determine the sign of a number in an RNS architecture thereby hampering the full implementation RNS in general purpose computing. In this paper, an efficient sign detection algorithm for detecting the sign of a number in an RNS architecture is presented. In formulating the algorithms, X maximum, (X max ) is computed from the Dynamic Range, M=∏ ki=1 (m i ). Modular Computation Technique is employed as a converter to compute X from the residues (r 1 , r 2 , r 3 ) with respect to a given moduli set, say (cid:1) = { (cid:2) 1 , (cid:2) 2 …, (cid:2) n }. X is positive if X-X max <0 otherwise X is negative and the actual value is this case is computed as X-M. The moduli set {2 n -1, 2 n , 2 n +1, 2 (n+1) -1, 2 2n -5} is used for the system design implementation and for numerical illustrations. It is observed that the scheme effectively detects the sign of RNS numbers and theoretical analysis showed that simple hardware resources and low-power modular adders are used in the design. It is also observed that the scheme when implemented practically can help project RNS to be used in general purpose computing.


Introduction
In recent times, there has been much growing interest in the study of Residue Number System (RNS) in the field of parallel computing.This can be significantly traced to the great deal of computing that takes place in embedded processors such as those found in mobile devices and signal processing which normally require high speed computations with low-power consumption.The absence of carry-propagation in RNS results in parallel computing that guarantees fault-tolerance, high-speed and low-power arithmetic.Today, computer chips have become so dense that full testing is no longer possible and therefore has made fault-tolerance and the general area of computational integrity essential.In Digital Computer Arithmetic, this kind of number representation introduces parallelism Paharmi [6], which is very useful in applications like cryptography Antao and Sousa [3] and Digital Signal Processing Soderstand et al., [7].Nonetheless, while operations such as addition, subtraction and multiplication may be carried out quickly and directly in parallel on the residues, additional arithmetic operations like reverse conversion, scaling, magnitude comparison and sign and overflow detection are challenging to implement in RNS Paharmi [6].Traditionally, investigations to detect the sign and compare the magnitude of numbers largely relied on RNS reverse conversion techniques such as the Chinese Remainder Theorem (CRT) and the Mixed Radix Conversion (MRC) [9].In this approach, numbers are translated from RNS into a positional number representation scheme where the comparison operation may be computed effectively.

Fundamentals of RNS
RNS is defined by a set S, of N integers that are pair-wise relatively prime.That is = { 1 , 2, …, n } where the greatest common divisor of any pair , is 1.That is gcd , = 1 for ,=1,..., and ≠ .In this case, every integer in [0, −1], can be uniquely represented with an N-tuple where, = ∏ is the dynamic range.For any integer X, we have X→ ( 1 , 2 ,…, ) and = | | = ( mod ); for =1 .The set S and the number are called the moduli set and residue of X modulo respectively.

Application of RNS
One major breakthrough in the study of RNS is the discovery of its ability to carry out high speed computation as well as perform parallel arithmetic and processing.These attributes have led to its adoption in Digital Signal Processing applications such as Digital Filtering, Discrete Cosine Transform (DCT), Discrete Fourier Transform (DFT), Fast Fourier Transform (FFT), Digital Communication and Error Detection and Correction.

Challenges of RNS
Generally, architectures built on RNS have great advantage in terms of speed, fault-tolerance and power management.This therefore has made it very suitable to implement RNS-based processors in different applications.However, in spite of these great advantages, RNS processors do not find wide range usage in practical computing due to some limiting factors that make the process very difficult.Some of these factors that have resulted in open research are: Conversion, Magnitude Comparison, Sign Detection and Overflow Detection among others.

Domain of the Research
In this research, we propose an efficient sign-detection-scheme by employing the modular computation technique as a converter in the field of Residue Number System.

Literature Review
In RNS, it is difficult to identify a negative number and many researchers have looked into sign detecting algorithms as an alternative.In Ulman [10], a sign detection algorithm for a certain class of RNS was proposed which uses a sum of modulo 2 of digits in the related Mixed Radix System (MRS).Vu [11] proposed a sign detection strategy based on fractional representation for reducing the total modulo M in the conversion formula to a sum modulo 2. Xu et al., Al-Radadi [2], presented a sign identification technique based on the new Chinese Remainder Theorem (CRT) II.The modulo operations in the sign detection algorithm have a large size of modulo M. Again, another sign detection approach by Akkal and Siy [1] uses the nth Mixed Radix Digit (MRD) in Mixed-Radix Conversion (MRC).Hiasat [4], proposed a residue-based sign detection scheme using carry-save and carry-generation circuits on a four-moduli set to enhance the performance of an arithmetic unit.This reduced the time delay by a large margin and performance analysis with a similar sign detector put the proposed converter ahead in time, area and power consumption.VLSI tools were used to experiment the scheme to confirm its gain.In all, the research promised to be relevant in applications requiring high speed, such as communication systems.Akkal and Siy [1] presented a generic sign detection algorithm based on the Mixed Radix Conversion algorithm, MRC-II.The algorithm uses only one step comparison for sign detection.The conversion algorithm works by eliminating the need for table lookup normally used in MRC hardware implementation and hence does not need ROM as in the case of other algorithms.A fast RNS sign detection algorithm for the restricted moduli set {2 -1, 2 +1, 2 + 1, 2 !} has also been discussed by Xu et al., [12].Their proposed algorithm allows for parallel implementation and consists exclusively of modulo 2n additions.The implementation of the algorithm has been done using one carry save adder, one comparator and one prefix adder.The experimental results showed that the proposed circuit unit had gained in area, delay and power by 63.8%, 44.9%, and 67.6% respectively when compared with a unit based on one of the best sign detection algorithms.In a paper authored by Antao and Sousa [3], a new approach was proposed for sign detection and number comparison using a revised version of the Mixed Radix Conversion (MRC) for an augmented 3-moduli sets {2 +1, 2 −1, 2 !}.Almost all their computations were directly performed on the moduli channels, allowing for easy use in any RNS processor.The paper further presented an efficient, unified and very large-scale integration architecture based on the proposed scheme and this was implemented using 65 nm CMOS technologies which showed that the proposed architecture was more efficient than some related state of the art architecture.Sousa and Martins [8] designed an efficient RNS comparators for large dynamic range and implemented it on the {2 n + 1, 2 n -1, 2 n+x } moduli set.The design technique followed a two-step approach.Firstly, the MRC was used to optimize the sign identification, by focusing on the extraction of the sign bit and on the parallelism of the hardware structure.The sign identification module was then used to implement the number comparison operation.The proposed comparator demonstrated to be a very attractive RNS-Based hardware architecture for signal processing applications.Hiasat [5] introduced a new architecture for sign detection for the moduli set #2 !$ , 2 − 1, 2 + 1, }, where n and p are positive integers such that p < n.The proposed decoder was seen to be flexible and efficient since it could easily deal with large dynamic range starting from 3n bits up to 3n + p bits dynamic range.For cases where p > 1, increasing the dynamic range by 1 bit (i.e., doubling the dynamic range) requires only one half-adder and no additional delay.When compared with the most competitive published work, the new sign detector exhibited a better performance in terms of area, delay and power that ranges from 4.7 percent up to 44.8 percent.Younes and Steffan [13] presented two designs for overflow and sign detection and correction in unsigned and signed RNS based on the moduli set {2n -1, 2n, 2n + 1}.This set has an even dynamic range.Moreover, these designs can be considered as universal, since they can be used with any system that has an even dynamic range by applying a small Technique for the Moduli Set {2 n -1, 2 n , 2 n +1, 2 (n+1) -1, 2 2n -5} modification on the evaluation unit.Both designs are faster and require less hardware components than those based on comparators.

Proposed Algorithm
In this section, we propose an efficient algorithm to determine the sign of an RNS number by dividing the procedure into two parts.In part one, we compute X max and then in part two, we compute the decimal equivalent, X of a given residue number, say X=&' , ' , … , ' ) with respect to the moduli set = # , , … , } using the modular computation technique as a converter.We then perform the necessary comparisons in order to determine the sign of the RNS number.The sign detection process is illustrated as follows: Compute X using the modular computation method as a reverse converter for a given residue number, X=&' , ' , … , ' ) with respect to the moduli set = # , , … , } Decision Whether Sign is Positive OR Negative If the decimal number, X computed is less than *+ then it is positive.
However, If the decimal number, X computed is greater than *+ then, we determine β=X-M.In this case β will be negative.

Modular Computation Technique
The Modular Computation Method is a fast but low power dispense Residue-to-binary conversion technique that employs modular computations in the reverse conversion process.Given a relatively prime moduli set # , , … , } and its corresponding residues&' , ' , … , ' ), we define the first jump , which is equal to the first residue ' , andas its first location given by: Finally, the corresponding decimal number X is the result of summing of the = G H, thus = = + = + ⋯ + =

Proposed Converter
The proposed algorithm using cyclic jump method is presented in details below: Given a 5-moduli set = #m , m , m J , m K , m L } such that #r , r , r J , r K , r L } are the residues of the decimal number X, then by the cyclic jump approach we have; 1 st Jump: J 1 = r 1 9 : = ' L 8 9 9 9 9 9 9 : = ' L 8 9 9 9 9 9 : 9 : , 0, 0, 0, 0) Finally, the corresponding decimal number X is the result of summing of the = G H, thus = = + = + = J + = K + = L

Implementation of the Algorithm on the Moduli Set
r 2 , r 3 , r 4 , r 5 ) are the residues of the decimal number X.
i.The first jump = is defined by the number which normally corresponds to the first residue in X.Thus = = 1.
The first location ^ is defined by ii. Second jump is defined by the number = , such that: The second location ^ is defined by iii.Third jump is defined by the number 9= J , such that: The third location ^J is defined by iv. Fourth jump is defined by the number = K , such that: The fourth location ^K is defined by Fifth jump is defined by the number = L , such that: The fifth location ^L is defined by Therefore, the corresponding equivalent decimal number X is: = + = + = J + = K + = L = 1 + 0 + 48 + 360 + 4200 = 4609 Thus &1, 1, 4, 3, 0 ) ghi = 4609 jkl *m .
i) The first jump = is defined by the number which normally corresponds to the first residue in X.Thus = = 2.
The first location ^ is defined by ii) Second jump is defined by the number = , such that: The second location ^ is defined by iii) Third jump is defined by the number = J , such that: Comparing the X computed and the *+ , We have 11 being less than 2309 as seen in Table 1, we do not subtract the dynamic range from the decimal number to get its equivalent sign number, instead we take the results.This indicates that, the number whose residues are &2, 3, 1, 4, 0 ) is 11.

Hardware Implementation of the Proposed Scheme
In Figure 1, it can be seen that the proposed scheme is a simple architecture built mainly on Carry Propagation modular Adders (CPA-modm), two Carry Save Adders (2 CSA S ), two Accumulators (2ACC S ) and one Multiplier (1MUX).In determining K n , the MUX and ACC are used whilst CPA-modms are used for all the modular computations in the conversion process.Also the CSA s are used in processing the final X for the sign detection.In Table 2, we compare the proposed scheme with the Chinese Remainder Theorem (CRT) and the Mixed Radix Conversion (MRC).It is observed that converters built around the CRT technology largely depend on the Dynamic Range (M) which is computationally intensive there by increasing the delay and power consumption.Similarly, converters built on the MRC are sequential in nature.Therefore, the computational processes are equally slow and Technique for the Moduli Set {2 n -1, 2 n , 2 n +1, 2 (n+1) -1, 2 2n -5} also inflict high power usage.In the proposed scheme, the conversion processes are dominated by modular computations which are traded for less delay, low power consumption and low cost (less resource requirements).

Conclusion
In this study, an efficient sign detection scheme in RNS has been proposed.The modular computation technique was used as a converter which resulted in high degree of parallelism and less computational intensity.Theoretical analysis showed that the scheme is advantaged with low power consumption, less delay and low cost of design.The scheme detects the sign of RSN numbers and can be implemented practically to help realize the dream of RNS being used in general purpose computing We continue finding the next jump and location and stop when B CD -EF B = 0 Such that n th location L n = |X -J n |=

Figure 1 .
Figure 1.Architecture for the Proposed Method.

Table 2 .
Comparing the Proposed Scheme with the CRT and MRC.